1. Field of the Invention
The present invention relates in general to integrated circuits, and more particularly to input buffers in memory circuits. Still more particularly, the present invention relates to address buffers.
2. Description of the Prior Art
Many modern integrated circuits are designed to perform their operations in response to input signals which are applied to terminals at relatively high frequencies and in an asynchronous or unclocked manner. One type of such integrated circuits is a static random access memory, commonly referred to as an asynchronous SRAM. Asynchronous SRAM's are designed to receive address values at address terminals, and to statically provide read or write access to the memory cells corresponding to the value of the address applied thereto. Accordingly, such asynchronous SRAM circuits are designed to quickly respond to the address value applied thereto, without relying on a clock signal indicating that the value at its address terminals is valid. In order to provide the performance benefits of internal dynamic operation, many modern asynchronous SRAMs include an address transition detection (ATD) circuit. The ATD circuit detects transitions at certain inputs to the SRAM, particularly the address terminals, and generates an internal signal responsive to detecting such a transition. The use of an ATD circuit allows the SRAM circuit to perform certain internal operations, such as precharging bit lines, deselecting sense amplifiers, and the like, after detection of the address transition, but before the decoders access the desired cell.
Address buffers are used, in conjunction with decoders, to select row or bit lines within a memory array during read and write operations. In particular, during a write cycle, an address value is applied and maintained to inputs of address terminals, and the input data bits are applied to data terminals of the memory. The write enable input of the SRAM is brought active to effect the write operation. The timing diagram of a typical write cycle is shown in FIG. 1. As can be seen, the address signals are setted at time t.sub.0 and must be held at same levels until the completion of write, for all the write cycle time t.sub.WC. Then, after a predetermined time, shown as setup time in FIG. 1, the write.sub.-- bar signal is brought low. This setup time is necessary to be sure that logic values at address inputs are valid and stable when the write signal is enabled. Analogously address values must be held at same levels for a hold time after the write.sub.-- bar signal returns high.
This timing, used in conventional asynchronous SRAM memories, can be a constraint for some systems (for example memory controllers and microprocessors) in which the requirement to maintain address signals for a long time can be a problem. Setup and hold times must be met which imposes more constraints on the system. Also, if the system operates in a noisy environment, the address signals may vary during the write cycle and cause an incorrect cell to be written. Indeed, it has been shown through testing, that the most critical operation mode that affects input levels is the write cycle, in which an unstable level can cause an incorrect cell to be written. Additional problems may also be caused by high frequency address transitions during a write operation, caused by noise at the address terminals of sufficient amplitude to cause a transition during such a write operation.
An example of an input buffer, designed to solve the problem of high frequency address transitions at the address terminals of a memory device is described in U.S. Pat. No. 5,124,584, entitled Address buffer circuit with transition-based latching, assigned to SGS THOMSON Microelectronics Inc., and incorporated herein by this reference. An input buffer, which includes an address transition detection (ATD) circuit, is disclosed therein. The input stage of this input buffer is connected to a delay stage, and to a transition detection circuit. The output of the delay stage is connected to a pass gate, which is controlled by the output of the transition detection circuit; a latch is connected to the other side of the of the pass gate. The transition detection circuit produces a pulse responsive to a transition, and the pass gate is turned off during the length of the pulse, with the latch maintaining and presenting the state of the input prior to the transition. After the pulse is complete, the new value of the input signal is latched and presented to the circuit. Since the pass gate is turned off during the transition detection pulse, a short and spurious transition at the input terminal is isolated from the latch by the pass gate, and does not appear at the output of the input buffer circuit.
The input buffer of U.S. Pat. No. 5,124,584, while solving the problem of high frequency address transitions, incorporates a transition detection circuit; such circuit is quite complicated and requires, on the integrated circuit, a relatively large area in relation to the area of a conventional input buffer. Moreover this input buffer is not capable to recover from variations of the input signal longer then a limited time and not impulsive. System still needs to meet address setup and hold times and maintain stable addresses for the duration of the write.
It is therefore an object of the present invention to provide an input buffer for an asynchronous integrated memory circuit which is immune from any kind of transitions on its input during most part of a write cycle.
It is a further object of the present invention to provide control of the input buffers of an asynchronous integrated memory circuit in such a manner that timing constraints during a write cycle are greatly alleviated or eliminated.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.